1. Field of the Invention
The subject invention relates generally to data conversion circuitry and in particular, to a differential comparator bank for use in an Analog to Digital Converter and other similar signal processing circuitry.
2. Description of Related Art
Low cost, relatively high speed, analog-to-digital converters (ADCs) have become critical building blocks for digital signal processing and video applications. By way of example, flash ADCs implemented in CMOS have been developed that are straightforward in design and are capable of high speed operation. However, an n bit flash ADC require 2.sup.n separate comparators for each output. Thus, an eight bit flash ADC will require 256 comparator circuits, thereby requiring a large die size, increased power consumption and large input loading.
Subranging ADCs have been developed to address some of the shortcomings of the flash ADC. The subranging ADC incorporates a resistor network for generating multiple coarse reference voltages used to determine the MSB outputs and multiple fine reference voltages used to determine the LSB outputs. The resistor network is typically connected between a pair of reference voltages such as a positive voltage and ground. By way of example, for an eight bit ADC, the coarse resistor network will have a total of 15 relatively low value resistance sections thereby providing 16 different taps where 16 different magnitude reference voltages are produced. The fine resistor network includes a relatively high impedance section connected in parallel across each of the relatively low impedance sections of the coarse resistor network. Each fine resistor section provides 15 taps so that 15 different magnitude reference voltages a produced having magnitudes that are intermediate the reference voltage drop across the associated coarse resistance section.
Each of the 16 resistance taps of the coarse resistance network has an associated CMOS comparator circuit which compares the magnitude of the reference voltage produced at the tap with the analog voltage to be measured. Thus, there are 16 comparator circuits (coarse comparators) associated with the coarse resistor network which produce 16 outputs received by an MSB encoder circuit. The MSB encoder circuit provides the four MSB outputs of the ADC.
There are 15 additional comparator circuits (fine comparators) which are connected by way of an analog multiplexer to the 15 taps of each of the fine resistor sections. The multiplexer selects one of the groups of 15 taps for connection to the fine comparators based upon the MSB determination in the previous clock cycle. Thus, at least two clock intervals (half clock cycles), and frequently more, are necessary for each measurement as compared to flash ADCs which require significantly fewer intervals. The outputs of the fine comparators are received by a second encoder circuit which produces the four LSBs of the ADC.
Although the subranging ADC is slower than the flash ADC, the number of comparators needed in the subranging ADC is reduced from 256 to 31. Thus, less die area is needed, lower power consumption is achieved and less loading is placed on the analog input.
In order to reduce the number of different reference voltages that need to be produced by the resistor network, subranging ADCs have been developed that include comparator banks that carry out an interpolation function. One such prior art ADC is disclosed in the IEEE Journal of Solid-State Circuits, Vol. 28, No. 12 dated December 1993 entitled "A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC" by Kusomoto et al. In addition to reducing the number of voltages that must be produced by the resistor network, the interpolation function as implemented reduces the number of amplifiers that must be used in the comparator bank thereby reducing the ADC power consumption. In addition, the reduced number of amplifiers lowers the capacitive loading on the input signal to the ADC. There is also an improvement in the differential non-linearity (DNL) of the ADC due to a redistribution of error voltages.
Although the conventional subranging ADCs provide several advantages over other types of ADCs, areas of needed improvement remain. Among the areas needing improvement are the comparator banks. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings, the present invention possesses significant advantages over the comparator banks used in such prior art ADCs.